Table of content

• 1. Introduction
• 2. Directory structure: openMSP430 core
• 3. Directory structure: FGPA projects
  • 3.1 Xilinx Spartan 3 example
  • 3.2 Altera Cyclone II example
  • 3.3 Actel ProASIC3 example
• 4. Directory structure: Software Development Tools

1. Introduction

To simplify the integration of this IP, the directory structure is based on the OpenCores recommendations.

2. Directory structure: openMSP430 core

core					openMSP430 Core top level directory
abcd	bench				Top level testbench directory
	abcd	verilog
		abcd	tb_openMSP430.v		Testbench top level module
			ram.v		RAM verilog model
			registers.v		Connections to Core internals for easy debugging
			dbg_uart_tasks.v		UART tasks for the serial debug interface
			dbg_i2c_tasks.v		I2C tasks for the serial debug interface
			io_cell.v		Generic I/O cell model for building the serial debug interface I2C bus
			msp_debug.v		Testbench instruction decoder and ASCII chain generator for easy debugging
			timescale.v		Global time scale definition for simulation.
	doc				Diverse documentation
	abcd	slau049f.pdf			MSP430x1xx Family User's Guide
	rtl				RTL sources
	abcd	verilog
		abcd	openMSP430_defines.v		openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration, ...)
			openMSP430_undefines.v		openMSP430 Verilog `undef file
			openMSP430.v		openMSP430 top level
			omsp_frontend.v		Instruction fetch and decode
			omsp_execution_unit.v		Execution unit
			omsp_alu.v		ALU
			omsp_register_file.v		Register file
			omsp_mem_backbone.v		Memory backbone
			omsp_clock_module.v		Basic Clock Module
			omsp_sfr.v		Special function registers
			omsp_watchdog.v		Watchdog Timer
			omsp_multiplier.v		16x16 Hardware Multiplier
			omsp_dbg.v		Serial Debug Interface main block
			omsp_dbg_hwbrk.v		Serial Debug Interface hardware breakpoint unit
			omsp_dbg_uart.v		Serial Debug Interface UART communication block
			omsp_dbg_i2c.v		Serial Debug Interface I2C communication block
			omsp_sync_cell.v		Simple synchronization module (double flip-flop).
			omsp_sync_reset.v		Generic Reset synchronizer (double flip-flop).
			omsp_clock_gate.v		Generic Clock gate (NAND2 or LATCH-AND based).
			omsp_clock_mux.v		Standard Clock Mux (used in the clock module & watchdog timer).
			omsp_and_gate.v		AND gate module used on sensitive glitch free data paths.
			omsp_wakeup_cell.v		Generic Wake-up module.
			omsp_scan_mux.v		Scan MUX.
			periph		Peripherals directory
			abcd	omsp_gpio.v	Digital I/O (Port 1 to 6)
				omsp_timerA_defines.v	Timer A configuration file
				omsp_timerA_undefines.v	Timer A Verilog `undef file
				omsp_timerA.v	Timer A
				template_periph_16b.v	Verilog template for 16 bit peripherals
				template_periph_8b.v	Verilog template for 8 bit peripherals
	sim				Top level simulations directory
	abcd	rtl_sim			RTL simulations
		abcd	bin		RTL simulation scripts
			abcd	msp430sim	Main simulation script for assembler vector sources (located in the src directory)
				msp430sim_c	Main simulation script for C vector sources (located in the src-c directory)
				asm2ihex.sh	Assembly file compilation (Intel HEX file generation)
				ihex2mem.tcl	Verilog program memory file generation
				rtlsim.sh	Verilog Icarus simulation script
				template.x	ASM linker definition file template
				template_defs.asm	Common ASM definition file included in all ".s43" files
				omsp_config.sh	oMSP configuration file.
				parse_results	Script parsing regression log files and generating summary report.
				cov_*	Code coverage scripts for NC-Verilog and ICM
			run		For running RTL simulations
			abcd	run	Run single simulation of a given assembler vector
				run_c	Run single simulation of a given C vector
				run_all	Run regression of all vectors
				run_all_mpy	Run regression of all hardware multiplier vectors (!!! very long simulation time !!!)
				run_disassemble	Disassemble the program memory content of the latest simulation
				run_coverage_analysis	Performs the coverage report merging of the regression run and starts ICM for the analysis.
load_waveform.sav				SAV file for gtkWave
src			RTL simulation vectors sources (ASM based)
abcd	ldscript_example.x		MSPGCC toolchain linker script example
	submit.prj		ISIM simulator verilog command file
	submit.f		Verilog simulator command file
	core.f		Command file listing the CPU files only.
	sing-op_*.s43		Single-operand assembler vector files
	sing-op_*.v		Single-operand verilog stimulus vector files
	two-op_*.s43		Two-operand assembler vector files
	two-op_*.v		Two-operand verilog stimulus vector files
	c-jump_*.s43		Jump assembler vector files
	c-jump_*.v		Jump verilog stimulus vector files
	nmi.s43		NMI assembler vector files
	nmi.v		NMI verilog stimulus vector files
	cpu_startup_asic.s43		CPU startup assembler vector files
	cpu_startup_asic.v		CPU startup stimulus vector files
	op_modes*.s43		CPU operating modes assembler vector files (CPUOFF, OSCOFF, SCG1)
	op_modes*.v		CPU operating modes verilog stimulus vector files (CPUOFF, OSCOFF, SCG1)
	clock_module*.s43		Basic Clock Module assembler vector files
	clock_module*.v		Basic Clock Module verilog stimulus vector files
	lp_modes_*.s43		Low Power modes assembler vector files
	lp_modes_*.v		Low Power modes verilog stimulus vector files
	dbg_*.s43		Serial Debug Interface assembler vector files
	dbg_*.v		Serial Debug Interface verilog stimulus vector files
	sfr.s43		SFR assembler vector files
	sfr.v		SFR verilog stimulus vector files
	gpio_*.s43		Digital I/O assembler vector files
	gpio_*.v		Digital I/O verilog stimulus vector files
	template_periph_*.s43		Peripheral templates assembler vector files
	template_periph_*.v		Peripheral templates verilog stimulus vector files
	wdt_*.s43		Watchdog timer assembler vector files
	wdt_*.v		Watchdog timer verilog stimulus vector files
	tA_*.s43		Timer A assembler vector files
	tA_*.v		Timer A verilog stimulus vector files
	mpy_*.s43		16x16 Multiplier assembler vector files
	mpy_*.v		16x16 Multiplier verilog stimulus vector files
	scan.s43		Scan test assembler vector files
	scan.v		Scan test verilog stimulus vector files
src-c			RTL simulation vectors sources (C based)
	coremark_v1.0		CoreMark benchmark
	dhrystone_v2.1		Dhrystone benchmark ("official" version)
	dhrystone_4mcu		Dhrystone benchmark (MCU adapted)
	sandbox		Small playground :-)
synthesis				Top level synthesis directory
abcd	synopsys			Synopsys (Design Compiler) directory
	abcd	run_syn		Run synthesis
		run_tmax		Run ATPG
		synthesis.tcl		Main synthesis TCL script
		library.tcl		Load library, set operating conditions and wire load models
		read.tcl		Read RTL
		constraints.tcl		Set design constrains
		tmax.tcl		Main TetraMax (ATPG) script.
		results		Results directory
	actel			Actel synthesis setup for area & speed analysis
	altera			Altera synthesis setup for area & speed analysis
	xilinx			Xilinx synthesis setup for area & speed analysis

3. Directory structure: FGPA projects

3.1 Xilinx Spartan 3 example

fpga							openMSP430 FPGA Projects top level directory
abcd	xilinx_diligent_s3_board						Xilinx FPGA Project based on the Diligent Spartan-3 board
	abcd	bench					Top level testbench directory
		abcd	verilog
			abcd	tb_openMSP430_fpga.v			FPGA testbench top level module
				registers.v			Connections to Core internals for easy debugging
				msp_debug.v			Testbench instruction decoder and ASCII chain generator for easy debugging
				glbl.v			Xilinx "glbl.v" file
				timescale.v			Global time scale definition for simulation.
		doc					Diverse documentation
		abcd	board_user_guide.pdf				Spartan-3 FPGA Starter Kit Board User Guide
			msp430f1121a.pdf				msp430f1121a Specification
			xapp462.pdf				Xilinx Digital Clock Managers (DCMs) user guide
		rtl					RTL sources
		abcd	verilog
			abcd	openMSP430_fpga.v			FPGA top level file
				driver_7segment.v			Four-Digit, Seven-Segment LED Display driver
				io_mux.v			I/O mux for port function selection.
				openmsp430			Local copy of the openMSP430 core. The *define.v file has been adjusted to the requirements of the project.
				coregen			Xilinx's coregen directory
				abcd	ram_8x512_hi.*		512 Byte RAM (upper byte)
					ram_8x512_lo.*		512 Byte RAM (lower byte)
					ram_8x2k_hi.*		2 kByte RAM (upper byte)
					ram_8x2k_lo.*		2 kByte RAM (lower byte)
		sim					Top level simulations directory
		abcd	rtl_sim				RTL simulations
			abcd	bin			RTL simulation scripts
				abcd	msp430sim		Main simulation script
					ihex2mem.tcl		Verilog program memory file generation
					rtlsim.sh		Verilog Icarus simulation script
				run			For running RTL simulations
				abcd	run		Run simulation of a given software project
					run_disassemble		Disassemble the program memory content of the latest simulation
				src			RTL simulation verilog stimulus
				abcd	submit.f		Verilog simulator command file
					*.v		Stimulus vector for the corresponding software project
		software					Software C programs to be loaded in the program memory
		abcd	leds				LEDs blinking application (from the CDK4MSP project)
			abcd	makefile
				hardware.h
				main.c
				7seg.h
				7seg.c
			ta_uart				Software UART with Timer_A (from the CDK4MSP project)
		synthesis					Top level synthesis directory
		abcd	xilinx
			abcd	0_create_bitstream.sh			Run Xilinx ISE synthesis in a Linux environment
				1_initialize_pmem.sh			Update bitstream's program memory with a given software ELF file
				2_generate_prom_file.sh			Generate PROM file
				3_program_fpga.sh			Program FPGA and on-board flash memory
				bitstreams
					*.bit		Bitstream files
					*.mcs		PROM files
					README.jpg		README file
				scripts
					ihex2mem.tcl		TCL script converting Intel-HEX format to Verilog memory file.
					impact_generate _prom_file.batch		iMPACT TCL script for PROM file generation.
					impact_program _fpga.batch		iMPACT TCL script for programing the FPGA and on-board flash memory.
					memory.bmm		FPGA memory description for bitstream's program memory update
					openMSP430_fpga.ucf		UCF file
					openMSP430_fpga.prj		RTL file list to be synthesized
					xst_verilog.opt		Verilog Option File for XST. Among other things, the search path to the include files is specified here.

3.2 Altera Cyclone II example

fpga							openMSP430 FPGA Projects top level directory
abcd	altera_de1_board						Altera FPGA Project based on Cyclone II Starter Development Board
	abcd	README					README file
		bench					Top level testbench directory
		abcd	verilog
			abcd	tb_openMSP430_fpga.v			FPGA testbench top level module
				registers.v			Connections to Core internals for easy debugging
				msp_debug.v			Testbench instruction decoder and ASCII chain generator for easy debugging
				altsyncram.v			Altera verilog model of the altsyncram module.
				timescale.v			Global time scale definition for simulation.
		doc					Diverse documentation
		abcd	DE1_Board_Schematic.pdf				Cyclone II FPGA Starter Development Board Schematics
			DE1_Reference_Manual.pdf				Cyclone II FPGA Starter Development Board Reference Manual
			DE1_User_Guide.pdf				Cyclone II FPGA Starter Development Board User Guide
		rtl					RTL sources
		abcd	verilog
			abcd	OpenMSP430_fpga.v			FPGA top level file
				driver_7segment.v			Four-Digit, Seven-Segment LED Display driver
				io_mux.v			I/O mux for port function selection.
				ext_de1_sram.v			Interface with altera DE1's external async SRAM (256kwords x 16bits)
				ram16x512.v			Single port RAM generated with the megafunction wizard
				rom16x2048.v			Single port ROM generated with the megafunction wizard
				openmsp430			Local copy of the openMSP430 core. The *define.v file has been adjusted to the requirements of the project.
		sim					Top level simulations directory
		abcd	rtl_sim				RTL simulations
			abcd	bin			RTL simulation scripts
				abcd	msp430sim		Main simulation script
					ihex2mem.tcl		Verilog program memory file generation
					rtlsim.sh		Verilog Icarus simulation script
				run			For running RTL simulations
				abcd	run		Run simulation of a given software project
					run_disassemble		Disassemble the program memory content of the latest simulation
				src			RTL simulation verilog stimulus
				abcd	submit.f		Verilog simulator command file
					*.v		Stimulus vector for the corresponding software project
		software					Software C programs to be loaded in the program memory
		abcd	bin				Specific binaries required for software development.
			abcd	mifwrite.cpp			This prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly changed to satisfy quartus6.1 *.mif eating engine.
				mifwrite.exe			Windows executable.
				mifwrite			Linux executable.
			memledtest				LEDs blinking application (from the CDK4MSP project)
		synthesis					Top level synthesis directory
		abcd	altera
			abcd	main.qsf			Global Assignments file
				main.sof			SOF file
				OpenMSP430_fpga.qpf			Quartus II project file
				openMSP430_fpga_top.v			RTL file list to be synthesized

3.3 Actel ProASIC3 example

fpga						openMSP430 FPGA Projects top level directory
abcd	actel_m1a3pl_dev_kit					Actel FPGA Project based on the ProASIC3 M1A3PL development kit
	abcd	bench				Top level testbench directory
		abcd	verilog
			abcd	tb_openMSP430_fpga.v		FPGA testbench top level module
				registers.v		Connections to Core internals for easy debugging
				msp_debug.v		Testbench instruction decoder and ASCII chain generator for easy debugging
				dbg_uart_tasks.v		UART tasks for the serial debug interface.
				timescale.v		Global time scale definition for simulation.
				proasic3l.v		Actel ProASIC3L library file.
				DAC121S101.v		Verilog model of National's DAC121S101 12 bit DAC.
		doc				Diverse documentation
		abcd	M1A3PL_DEV_KIT_QS.pdf			Development Kit Quickstart Card.
			M1IGLOO_StarterKit_v1_5_UG.pdf			Development Kit User's Guide.
		rtl				RTL sources
		abcd	verilog
			abcd	openMSP430_fpga.v		FPGA top level file
				dac_spi_if.v		SPI interface to National's DAC121S101 12 bit DAC.
				smartgen		Actel's smartgen directory.
				abcd	dmem_128B.v	128 Byte RAM (for data memory).
					pmem_2kB.v	2 kByte RAM (for program memory).
				openmsp430		Local copy of the openMSP430 core. The *define.v file has been adjusted to the requirements of the project.
		sim				Top level simulations directory
		abcd	rtl_sim			RTL simulations
				bin		RTL simulation scripts
					msp430sim	Main simulation script
					ihex2mem.tcl	Verilog program memory file generation
					rtlsim.sh	Verilog Icarus simulation script
				run		For running RTL simulations
					run	Run simulation of a given software project
					run_disassemble	Disassemble the program memory content of the latest simulation
				src		RTL simulation verilog stimulus
					submit.f	Verilog simulator command file
					*.v	Stimulus vector for the corresponding software project
		software				Software C programs to be loaded in the program memory
			spacewar			SpaceWar oscilloscope game.
		synthesis				Top level synthesis directory
		abcd	actel
			abcd	prepare_implementation.tcl		Generate required files prior synthesis and P&R.
				synplify.tcl		Synplify template for the synthesis run.
				libero_designer.tcl		Libero Designer template for the P&R run.
				design_files.v		RTL file list to be synthesized.
				design_constraints.pre.sdc		Synthesis timing constraints.
				design_constraints.post.sdc		P&R timing constraints.
				design_constraints.pdc		P&R physical constraints.

4. Directory structure: Software Development Tools

tools				openMSP430 Software Development Tools top level directory
abcd	omsp_alias.xml			This XML file allows the software development tools to identify a openMSP430 implementation, and add customized extra information (Alias, URL, ...).
	bin			Contains the main TCL scripts (and the windows executable files if generated)
	abcd	openmsp430-loader.tcl		Simple command line boot loader
		openmsp430-minidebug.tcl		Minimalistic debugger with simple GUI
		openmsp430-gdbproxy.tcl		GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends
		README.TXT		README file regarding the use of TCL scripts in a Windows environment.
	lib			Common library
	abcd	tcl-lib		Common TCL library
		abcd	dbg_uart_generic.tcl	Low level Generic UART communication functions
			dbg_i2c_usb-iss.tcl	Low level I2C communication functions for the USB-ISS adapter
			dbg_utils.tcl	Low level "COMx:" "/dev/tty" communication functions
			dbg_functions.tcl	Main utility functions for the openMSP430 serial debug interface
			combobox.tcl	A combobox listbox widget written in pure tcl (from Bryan Oakley)
			xml.tcl	Simple XML parser (from Keith Vetter)
	openmsp430-gdbproxy			GDB Proxy server main project directory
	abcd	openmsp430-gdbproxy.tcl		GDB Proxy server main TCL Script (symbolic link with the script in the bin directory)
		server.tcl		TCP/IP Server utility functions. Send/Receive RSP packets from GDB.
		commands.tcl		RSP command execution functions.
		doc		Some documentation regarding GDB and the RSP protocol.
		abcd	ew_GDB_RSP.pdf	Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol
			Howto-GDB_Remote_Serial_Protocol.pdf	Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server